Abstract

As integrated circuit (IC) power density increases and high-power burst applications emerge, circuit and layout designs must account for thermal behavior and heat dissipation. Proper matching of analog and mixed-signal components under high thermal conditions is crucial. This paper presents a voltage regulator in a Power-Over-Ethernet (POE) IC designed for high-power events. The regulator's thermal sensitivity and resilience to thermal gradients were analyzed and measured experimentally. A thermal-aware methodology was developed for its electrical and layout design, optimizing matched devices to mitigate thermally induced power fluctuations. The POE IC, fabricated using the TS35PM Tower Jazz process, was tested for performance and immunity to thermal bursts.

Key words: Thermal gradient, modeling heat dissipation, thermal awareness, linear regulator, Power-Over-Ethernet.